1. Field of the Invention
One or more embodiments of the present invention relate generally to a method for design partitioning at the behavioral circuit design level whereas hardware description language (HDL) of a design is processed according to partition specifications.
2. Background Art
Microelectronic circuits may consist of many million transistors and other electronic elements as a direct result of ever decreasing feature size and added circuit functionality. At the same time the processing steps required to manufacture such electronic circuits have increased as well, leading to longer manufacturing cycles. Consequently, to avoid any unnecessary delay in getting a new product to market, it is of utmost importance that the microelectronic circuits are well-designed and that any potential timing weakness has been identified and rectified before actual lithographic masks are produced.
The particular design specialty that is concerned with functional verification and timing verification is referred to as physical design and verification. There are several aspects of the microelectronic circuit design that present challenges to physical design and verification. One of these challenges results from the constrained amount of physical space that is allocated on a silicon wafer for an individual silicon die. As the cost for purchasing and processing a silicon wafer is essentially fixed, it is largely the individual silicon die size that determines how many chips can be obtained from a single wafer. The smaller the individual silicon die size, the more chips fit physically on a single wafer and thus, the average price per individual silicon die decreases.
To minimize the die size, floorplanning is concerned with the optimal physical placement of circuit design sections. However, optimal placement and routing from a purely geometric perspective results in hierarchies which are non-optimized from a timing verification perspective. The hierarchies obtained this way can result in circuits which are too large for the special tools used in design verification because the design verification processing time increases significantly with increasing circuit size.